The Roadmap for Multicore Hardware

The Roadmap for Multicore Hardware

Amador Rafiq A&D Field Application Engineer / Microchip Technology

Managing Memory Interference on Heterogeneous MPSoC: Challenges and Industry-oriented Approaches

Dr. Andrea Bastoni CTO / Minerva Systems, Italy

Is Robust Partitioning achievable with a multi-core system?

Karl Thyssen Senior Multicore Engineer / Rapita Systems Ltd, UK

Freedom From Interference for Multi-core Processor System

Michael Chapman CEO / Cortus, France

Is Robust Partitioning achievable with a multi-core system?

Olivier Charrier Principal Technologist – Functional Safety / Wind River

The multicore hardware roadmap focuses on delivering deterministic, safety-certifiable processors that meet escalating performance requirements without sacrificing reliability. Hardware designers must implement robust spatial and temporal isolation, minimize core and shared resource interference, and comply with DO-254, CAST-32A, and AMC 20-193 standards. Critical questions remain: Is current hardware sufficiently mature for safety-critical certification? How are suppliers ensuring long-term availability, configurability, and comprehensive toolchain support? What future and upcoming technologies can provide complete or partial solutions to these challenges? As performance demands grow and costs rise, can hardware innovation keep pace with the avionics industry’s stringent needs for predictability, traceability, and certifiability?