Michael Chapman
- CEO
- Cortus, France
Mike has been designing processors for most of his career. He started off working on the ALU for a military processor chip-set in 4um Silicon-On-Saphire (SOS) drawing transistor layouts by hand on graph paper with coloured pencils.
He developed the first ever CAN chip for Intel and then at Bosch he developed different CAN implementations for Phillips, Motorola, National Semiconductor, NEC and a second standalone CAN chip for Intel.
He went on to create derivatives of the Intel 82196 MCU family for Bosch for ABS, TCS and Engine management and the Siemens C167 derivative of the C166 family – all with CAN of course.
At Siemens he was chief architect for the second generation of the Siemens 16-bit CPU. A by-product of this development was System-C which is widely used today.
After a brief spell working on multi-core Sparclet network processor chips he founded Cortus in 2005 and created a highly efficient 32-bit core for embedded processing. This core and its derivatives are now found in 18 billion products and have a run rate of 1.2 billion devices per year.
The more recent activity of Cortus includes the development of RISC-V processors for nuclear, space, avionics and for the car industry ranging from simple MCUs for automotive body control to very high performance high end multi-core systems.
Sessions
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The Roadmap for Multicore Hardware
Freedom From Interference for Multi-core Processor System
The multicore hardware roadmap focuses on delivering deterministic, safety-certifiable processors that meet escalating performance requirements without sacrificing reliability. Hardware designers must implement robust spatial and temporal isolation, minimize core and shared resource interference, and comply with DO-254, CAST-32A, and AMC 20-193 standards. Critical questions remain: Is current hardware sufficiently mature for safety-critical certification? How are suppliers ensuring long-term availability, configurability, and comprehensive toolchain support? What future and upcoming technologies can provide complete or partial solutions to these challenges? As performance demands grow and costs rise, can hardware innovation keep pace with the avionics industry’s stringent needs for predictability, traceability, and certifiability?